For low-speed transactions the extra retry s allow a transaction additional chance s to recover regardless of if the full-speed transaction has errors or not. The contents of this More information. A USB low-speed transaction with errors, or the first retry of the transaction occurs near the end of a microframe, and there is not enough time to complete another retry of the low-speed transaction in the same microframe. Intel has only observed these implications with high resolution USB 3. Verifying Installation of the Software 8. The xx PLC may contain design defects or errors known as errata that.

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All opinions, More information. The xhci controller may also place a pointer to that memory in the event ring, causing the xhci driver to access that memory and process its contents, resulting in system hang, failure to enumerate devices, or other anomalous system behavior.

Intel(R) 8 Series/C220 Chipset Family SATA AHCI Controller

To use this website, you must agree to our Privacy Policyincluding cookie policy. System software may be unable to prevent xhci port USB 2. Current characterized errata are available on request.

No license express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document. Posted March 29, Posted September 27, Intel 5 Series Chipset and Intel Series Chipset may contain design defects or errors known as errata which More information.


Intel has only observed this failure when using software that does not comply with the USB specification and violates the hardware isochronous scheduling threshold by terminating transactions that are already in progress 4. Specification Changes are modifications to the current published specifications.

If there is other pending low-speed or full-speed transactions, the RMH will drop the isochronous transaction and resume normal operation.

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A BIOS code change has been identified to reduce the occurrence and may be implemented as a mitigation for this erratum. There is pending USB full-speed traffic and there is enough time fmily in the microframe to complete one or more attempts of the full-speed transaction.

Contact your Intel representative for possible mitigation. Uninstalling the Software The xhc will continue to try to initiate U3.

System Software can detect the timeout and perform a host controller reset to avoid the chioset hang. The small window of exposure for full-speed device is around 1. Identifying the Software Version Number Posted July 14, Enumeration Issue when Resuming for Sx If a device is attached while the platform is in S3 or S4 and the device is assigned the highest assignable Slot ID upon resume, the xhc may attempt to access an unassigned main memory famiily.


It described the More information.

Periodic transfers may be delayed or aborted. The xx PLC may contain design defects or errors known as errata that. Posted February 10, There are no known cases of data loss since the SuperSpeed device always re-enumerates.

Software knows which command was issued and which fields are valid to check for the event. The PCIe link may report link errors or train to a lower speed.

Bug# supplement to installation-report

Specification Change that applies to the stepping indicated. Contrroller xhci Ports may become non-functional. Posted October 21, No mark or Blank box: Intel has only observed the issue in a synthetic test environment where precise control of packet scheduling is available, and has not observed this failure in its compatibility validation testing. Legal Notices and Disclaimers. In some cases, the xhci controller may read de-allocated memory pointed to by a TRB of a disabled slot.

Intel Solid State Drive Toolbox 3.